Embodiments of the invention relate generally to semiconductor device packages or electronics packages and, more particularly, to an electronics package that includes an integrated interconnect structure formed from an insulating material that is metalized to include one or more electrical traces, which extend through the body of the electronics package to electrically connect contact pads on the die to contact terminals on the opposing side of the electronics package.
State of the art electronics packaging covers a wide range of methods, structures, and approaches from wire bond modules to flip chip modules and to embedded chip modules. Wire bonded modules are a mature packaging approach that is low cost but has limited electrical performance. These modules use wires bonded to chip pads to connect the top I/O pads of power devices to an interconnect structure such as a metal-insulator-metal substrate such as ceramic, Aluminum Nitride (AlN), or Silicon Carbide (SiC) substrate with patterned metal on top and bottom. Wire bonds have inherently high inductance, generally high series resistance, current crowding on the bond pads, and microcracking within the semiconductor devices near bonding sites. An exemplary construction of a prior art wire bond electronics package 10 is illustrated in FIG. 1 with two power semiconductor devices 12 mounted onto a leadframe 14 using die attach material 16. Portions of the leadframe 14 extend beyond the molding resin 26 forming terminals 18. Wire bonds 20 connect die pads 22 located on the active surface 24 of semiconductor devices 12 to selected areas on the leadframe 14. Molding resin 26 encapsulates semiconductor devices 12, wire bonds 20, and exposed portions of leadframe 14. PowerRibbon© Bonding (K&S) is a modified version of power module wire bonding that replaces Al wire bonds with Al ribbons that use thermos-compression to bond to the chip pads. Beneficially, PowerRibbon© Bonding has lower resistance and therefore is targeted for higher current modules. However, PowerRibbon© Bonding has high inductance and can cause substrate microcracking.
Prior art flip chip modules experience reduced semiconductor module damage as compared to wire bond packages through the use of solder bumps, which have larger current carrying cross-sections than wire bonds. A general construction of a prior art flip chip electronic package 28 is illustrated in FIG. 2 with two semiconductor devices 12 attached to a top side metal layer 30 of substrate 32 by means of flip chip solder bumps 34. Thermal cooling is achieved with thermal connections 36 formed on the back side 38 of semiconductor devices 12. Molding resin 26 encapsulates the semiconductor devices 12, with portions of the top side metal layer 30 extending beyond the molding resin 26 forming terminals 18. While flip chip modules such as that illustrated in FIG. 2 provide some advantages over wire bond technology, the flip chip solder bumps have poor electrical conductivity, require additional pad metallization layers to apply solder bumps, are susceptible to solder fatigue, and provide a very poor thermal cooling pathway.
Prior art embedded device modules, such as the embedded device module 40 illustrated in FIG. 3 fabricated using General Electric Company's power overlay (POL) technology, address the limitations of wire bond and flip chip packages by eliminating wire bonds and solder bumps and replacing them with direct metallization contacts. In the embedded device module 40, semiconductor devices 12 are mounted onto a dielectric film 42. A post connector 44 is also attached to the dielectric film 42 to provide a top-to-bottom electrical connection for the module 40. Microvias 46 are formed through the dielectric film 42 to the input/output (I/O) contact pads 22 of semiconductor devices 12 and to the post connector 44. A metallization layer 48 is applied to the outer surface of the dielectric film 42, the microvias 46 and the exposed pads 22 to form an electrical connection to the semiconductor devices 12. The dielectric film 42 with attached semiconductor devices 12 and post connector 44 is bonded to a power substrate 32 using an electrically conductive die attach material 50 such as solder. The gaps between semiconductor devices 12 and post connector 44 are filled with a molding resin 26. The embedded device module 40 has reduced parasitics (e.g., resistance, capacitance, and inductance) and a superior thermal performance as compared to wire bond modules or flip chip modules.
Despite the advantages of an embedded device module construction, POL technology is more complex, less mature, and higher cost than wire bond and flip chip approaches. Electrical connections within the module 40 are typically formed by either forming through holes in the module 40 using laser drilling and hole metallization or by forming a via to an inserted I/O structure or frame adjacent to the device that provide vertical connections. These approaches increase the complexity and cost of the module and can increase the module footprint.
Accordingly, it would be desirable to provide a new electronics packaging technology that permits construction of a highly miniaturized electronics package that allows for high pitch or high pin count applications and that provides an electrical connection between the bottom surface of the electronics package to the top of the semiconductor device or to an upper layer of the electronics package. Further, it would be desirable to have a packaging approach that has the performance and reliability advantages of embedded chip modules and the lower costs of wire bond or flip chip modules.